Clock Tree Synthesis and Floorplanning Interview Questions

Someone hands you a block with six hard macros and says the clock tree came back with bad skew. Where do you start? Many candidates jump straight to the clock tree. A better answer often begins earlier, with where the macros sit and how the sinks are spread around them.

Physical design interviews tend to reward people who can connect floorplan, placement, and clock decisions into one story. This guide draws on the public documentation of the open source OpenROAD project (floorplan, macro placement, power grid, global placement, and clock tree modules) and a university lecture page from UMBC on clock skew and timing. The practice prompts are ours, not questions reported from any employer. Commercial tools differ in commands and defaults, so treat this as concepts, not a recipe.

Floorplanning: size, shape, and what gets placed first

The OpenROAD floorplan documentation describes two ways to set the outline. You can give a utilization and an aspect ratio, where core area is design area divided by utilization and aspect ratio is height over width, or you can give explicit die and core coordinates. It warns against mixing them.

An interviewer who asks how you pick the aspect ratio is rarely looking for a number. Talk about what constrains the shape: where the IO pins need to land, how the macros pack, and the top-level plan. Say you would start from a utilization target, check how much room the macros leave for standard cells, and revisit it if congestion shows up later.

The OpenROAD macro placer documentation describes a cost built from wirelength, area, boundary distance, and other terms, with minimum channels between macros. The practical point: macros need room around them for routing and power connections, and macros that talk to each other usually belong near each other. Our VLSI physical design question guide covers the standard floorplan questions.

Power grid and IO choices affect everything downstream

The OpenROAD power grid documentation explains that standard cell rails follow the cell rows, while stripes have a chosen width, pitch, and offset, and rings can wrap a region. It also describes a routing tradeoff: via stacks on wide metal can block adjacent routing tracks. The page does not discuss IR drop, so connect that part yourself.

A strong answer names the tension: a denser grid helps voltage drop but takes routing resources, and a sparse grid does the opposite. For voltage drop in depth, see our power integrity and PDN guide.

Placement and congestion

The OpenROAD global placement documentation describes a timing-driven mode that reweights low-slack nets and a routability-driven mode that estimates congestion and inflates the area of cells in congested tiles. The placer also reports a target density, which defaults to 0.7 in that tool.

Congestion questions usually ask for a diagnosis. Say what you would look at: a congestion map, whether hot spots sit between macros or near a pin cluster, and whether utilization is simply too high. Then list fixes in order of cost: blockages or padding, macro moves, looser utilization, and only then a floorplan change. That ordering shows judgment.

What are the goals and tradeoffs of clock tree synthesis?

The UMBC lecture defines skew as the difference in clock arrival time between a destination register and a source register. Positive skew, where the destination clock arrives later, gives setup more time but hurts hold. Negative skew does the opposite for setup and also makes hold harder. Its slack equations add skew to setup slack and subtract it from hold slack. It notes that short paths with large skew are the likeliest hold problems, and that hold can be fixed by slowing the data path.

The OpenROAD clock tree documentation shows what a tool does about this. It can pre-cluster sinks and build an H-tree over the clusters, insert delay buffers to balance latency between macros and registers, add dummy loads to balance leaf loads, apply wider spacing to clock nets, and count levels across clock gates so a gated branch lines up with its parent.

Useful skew is the deliberate version: borrow time from a neighboring stage to fix a setup path, and pay in hold. For the power side of clock gating, see our low power design guide.

Topic	What the source says	Practice prompt
Aspect ratio	Height over width, set with utilization or explicit coordinates	What would make you change the shape of a block?
Macro placement	Cost balances wirelength, area, and channels between macros	How much space do you leave between two macros, and why?
Power grid	Stripe pitch and width trade against routing tracks	What happens to routing if you double the stripe density?
Congestion	Congested tiles get cell inflation during placement	How do you tell a utilization problem from a pin problem?
Skew	Positive skew helps setup and hurts hold, per UMBC notes	Which paths get worse if you add delay to a capture clock?
CTS balancing	Delay buffers and dummy loads balance latency and leaf load	Why would a macro have a different insertion delay than a flop?

An illustrative scenario: high skew after CTS

This one is ours. A block with several macros shows large skew between macro clock pins and the register sinks after CTS, and new hold violations appear.

1. Ask what the skew target and insertion delay goals are, and whether macro clock pin insertion delay is modeled in the tool.
2. Check the clock report for which sinks sit at the latency extremes before changing anything.
3. Look at the floorplan: are the macros clustered at one edge, forcing long clock wires to distant registers?
4. Consider balancing options such as delay buffers for macro sinks, and confirm clock gating cells are balanced against ungated flops.
5. Rerun, then compare setup and hold. Hold fixes add buffers on short data paths, so check area and power.

For the timing side of that last step, see our static timing analysis questions and the physical design versus signoff engineer comparison.

What does a good answer sound like?

Good answers state assumptions first, name the tradeoff, and say what data they would pull. Weak answers recite a definition and stop. If you have not used a commercial tool, say so, then describe the flow you did use. Our guide to explaining past projects can help you structure a short story.

If you want to rehearse a floorplan and CTS walkthrough out loud, you can book a mock interview on MockVise.

Sources: OpenROAD floorplan (ifp), OpenROAD macro placement (mpl), OpenROAD power grid (pdn), OpenROAD global placement (gpl), OpenROAD clock tree synthesis (cts), UMBC timing analysis lecture. This article provides general technical preparation guidance, not company interview questions or a tool tutorial. Defaults and options cited come from one open source tool and differ in commercial flows. Confirm the interview format with your recruiter. MockVise is not affiliated with or endorsed by the OpenROAD project or UMBC.

FAQ

Q: Where should I start when a block has bad clock skew after CTS? Check the clock report for which sinks sit at the latency extremes, then look at the floorplan. Macros clustered at one edge can force long clock wires to distant registers, so the fix may begin earlier than the clock tree.

Q: How does skew affect setup and hold? Per the UMBC lecture, positive skew gives setup more time but hurts hold, and negative skew does the opposite for setup while also making hold harder. Short paths with large skew are the likeliest hold problems.

Q: How do I answer a congestion question? Say what you would look at: a congestion map, whether hot spots sit between macros or near a pin cluster, and whether utilization is simply too high. Then list fixes in order of cost: blockages or padding, macro moves, looser utilization, and only then a floorplan change.

Q: What if I have not used a commercial EDA tool? Say so, then describe the flow you did use. The guide draws on the open source OpenROAD project, and commercial tools differ in commands and defaults, so treat it as concepts, not a recipe.