Power Integrity and PDN Interview Questions: Decoupling, IR Drop, and Impedance

A board passes its power simulation, then the chip resets when one workload starts. The rail looks fine on the bench meter. What would you measure next, and why did the simulation miss it?

For a power integrity, board design, or validation role, that kind of question is worth rehearsing. This guide draws on Xilinx application note XAPP623 on bypass and decoupling networks, a 2006 IEEE paper on decoupling capacitors from the University of Rochester, and a DesignCon 2021 paper on capacitor optimization by Mayo Clinic engineers. The practice prompts are ours, not questions reported from any employer.

What is target impedance, and what does it assume?

The Rochester paper gives target impedance as the allowed ripple voltage divided by the current. Its example assumes about 5% of the supply is permitted as ripple. It adds that the target must hold "not only at DC, but also at all frequencies where current transients exist."

Xilinx takes the maximum ripple from the datasheet to get a target impedance as a function of frequency.

A good opening answer names the inputs: "I would ask what ripple the device tolerates and what transient current it can draw, and over which frequencies." Xilinx notes that an FPGA's transient demand is hard to predict, so a first design is a conservative worst case.

The capacitor hierarchy, in numbers you can defend

The Rochester paper describes a hierarchy. A voltage regulator module works up to about 1 kHz, bulk capacitors cover roughly 1 kHz to 1 MHz, ceramic capacitors cover 1 MHz to several hundred MHz, and on-chip capacitors can help above 100 MHz. Treat those as one paper's example, not universal limits.

Xilinx aims for a low, flat impedance from about 500 kHz to 500 MHz, with at least one capacitor value per decade, and it suggests roughly doubling the count for each decade down in size. It also asks for one bulk value in the 470 uF to 1000 uF range. Higher-ESR bulk parts are effective over a wider band and less likely to cause anti-resonance spikes.

One detail interviewers can probe: the datasheet self-resonant frequency is not what you get on the board. Xilinx's example is a 0.01 uF ceramic with 0.9 nH of its own inductance. Adding 0.8 nH of mounting inductance moves resonance from 53 MHz to 38 MHz. It puts via inductance at 300 pH to 1,500 pH on a 60 mil board, so mounting matters.

Why do good-looking networks fail at anti-resonance?

Two capacitors in parallel can create a peak. The Rochester paper explains it this way: over some frequency range one capacitor has turned inductive while the other is still capacitive, so the pair forms an LC tank. That peak is called antiresonance. Its remedy is to add a smaller capacitor in parallel, which shifts the spike higher, or to lower the capacitor's inductance.

Xilinx describes a related case: a low-impedance, high-Q plane capacitance meeting the high-frequency discrete capacitors, which can produce a large noise voltage if the device draws current at that frequency.

The Mayo paper adds a caution. Meeting the target impedance is "only part of the equation." It prefers a flat impedance profile over high-Q peaks, and it says static voltage matters too. None of the three sources defines IR drop, so keep your own answer simple: current times resistance in the supply path, a DC effect, separate from the frequency-dependent behavior above.

The Mayo paper also uses "droop" in two ways: transient droops from poorly chosen capacitors, and active voltage positioning, also called droop or load-line. Ask which one is meant.

Turn the sources into a study plan

The technical distinctions below come from the three papers. The practice prompts are MockVise's suggested exercises, not an employer's interview rubric.

Topic	Documented distinction	Practice prompt
Target impedance	Ripple divided by current, needed at all transient frequencies, not just DC	What inputs would you request before computing it?
Hierarchy	Regulator, bulk, ceramic, and on-chip capacitors cover different bands	Which stage covers a 10 MHz load step?
Mounted resonance	Mounting inductance lowers resonance below the datasheet value	Why does placement change a capacitor's usefulness?
Anti-resonance	Parallel capacitors can form a peak; a smaller capacitor shifts it higher	How would you find and reduce one?
Impedance versus time domain	Meeting target impedance does not guarantee the lowest worst-case noise	What test would you run after the frequency sweep?
Droop	Can mean a transient dip or an intentional load-line	Which meaning does the interviewer intend?

Walk through a debugging scenario

Here is an illustrative scenario, our suggestion and not a standard procedure: a board resets under one workload, while a static rail check looks normal.

1. Confirm the failure is repeatable and note the workload that triggers it.
2. Measure the rail at the load, not at the regulator, during that workload.
3. Compare any ripple frequency you see against the impedance profile.
4. Check mounted inductance: via length, land geometry, and distance from the device.
5. Change one thing, such as a capacitor value or placement, and repeat the same workload.

Xilinx describes a similar loop. A network analyzer measures the impedance profile, a spectrum analyzer measures the voltage, and the two together indicate transient current as a function of frequency. It also lists other causes worth checking: noise from other devices on shared planes, and too much parasitic inductance between capacitor and device.

If the rail problem is really a timing problem, our static timing analysis guide can help you separate the two. For the broader lab conversation, see pre silicon verification versus post silicon validation.

Connect it to the rest of your preparation

A supply problem can look like a link problem, so our SerDes and signal integrity guide pairs well with this one. If the role also touches power domains and gating, read our low power design interview guide.

Pick a project you can discuss without confidential details, and organize it with our guide to explaining past projects. If you have never designed a PDN, say that plainly and describe what you would measure. You can book a mock interview on MockVise to practice explaining an impedance plot and defending your next change.

Sources: Xilinx XAPP623 (hosted copy), Popovich and Friedman, IEEE TVLSI 2006, Keuseman et al., DesignCon 2021. This article provides general technical preparation guidance, not company interview questions or a design procedure. Interview formats vary, so confirm yours with your recruiter, and check numbers against current vendor documentation. MockVise is not affiliated with or endorsed by AMD (Xilinx), IEEE, the University of Rochester, or Mayo Clinic.

FAQ

Q: Why does capacitor mounting matter? The datasheet self-resonant frequency is not what you get on the board. In Xilinx's example, adding 0.8 nH of mounting inductance to a 0.01 uF ceramic with 0.9 nH of its own inductance moves resonance from 53 MHz to 38 MHz.

Q: How do you reduce an anti-resonance peak? The Rochester paper says to add a smaller capacitor in parallel, which shifts the spike higher, or to lower the capacitor's inductance.

Q: Does meeting target impedance guarantee a good PDN? No. The Mayo paper says it is only part of the equation. It prefers a flat impedance profile over high-Q peaks, and it says static voltage matters too.

Q: What does "droop" mean in a PDN discussion? The Mayo paper uses it in two ways: transient droops from poorly chosen capacitors, and active voltage positioning, also called load-line. Ask which one the interviewer means.