VLSI Physical Design Interview Questions (2026 Guide)

Physical design (PD) is where RTL becomes silicon. A PD engineer takes a synthesized netlist and turns it into a manufacturable layout that meets timing, power, and area across every process corner — then signs it off for tape-out. The interviews reflect that end-to-end responsibility, moving through the full RTL-to-GDSII flow.

This guide covers the questions asked most often for PD roles at companies like Intel, AMD, NVIDIA, Qualcomm, and Apple. For the upstream design side, see our RTL design interview guide; for the role comparison, see FPGA vs ASIC.

The flow: know it end to end

1. Walk me through the RTL-to-GDSII flow.

This is the canonical opener. A strong answer hits the stages in order: synthesis → floorplanning → power planning → placement → clock tree synthesis (CTS) → routing → signoff (timing, physical verification, and extraction). For each stage, be able to state the goal and the main checks. Interviewers use your fluency here to gauge seniority instantly.

Floorplanning and power

2. What makes a good floorplan?

A good floorplan minimizes wire length and congestion, places macros (SRAMs, IP) sensibly at the edges or in channels, keeps related logic together, leaves room for the clock tree and power grid, and respects I/O placement. Bad floorplans cause congestion and timing problems that no amount of downstream effort can fully fix — "garbage in, garbage out."

3. What is utilization, and what's a typical target?

Utilization is the ratio of standard-cell area to available core area. Typical starting targets are around 60–75%. Too high and you get routing congestion and no room for buffers; too low wastes area and lengthens wires.

4. How is the power grid designed, and what is IR drop?

The power distribution network (rings, straps, and rails) delivers current to every cell. IR drop is the voltage loss across the resistance of that network; excessive IR drop slows cells and can cause functional failures. You manage it with adequate metal width, more straps, and decoupling capacitors.

Placement and CTS

5. What does the placement stage optimize, and what is congestion?

Placement positions every standard cell to minimize timing-critical wire length and routing congestion while honoring density and legality. Congestion is when more routing is demanded in a region than the available tracks can supply — a congestion map highlights hotspots you fix by spreading cells, adjusting the floorplan, or cell padding.

6. What is clock tree synthesis, and what are skew and insertion delay?

CTS builds the network that distributes the clock to every sequential element. Skew is the difference in clock arrival times between flops; insertion delay (latency) is the delay from the clock source to the flops. CTS aims to balance skew (often near zero, or useful skew to help timing) while controlling latency, using buffers and clock-gating cells.

7. Why insert clock gates during CTS, and what is a useful-skew strategy?

Clock gating saves dynamic power by stopping the clock to idle registers. Useful skew deliberately delays or advances certain clock arrivals to borrow time across a critical path — relaxing a tight setup path at the cost of hold margin elsewhere. Modern tools optimize skew per-path rather than forcing zero skew everywhere.

Routing and signoff

8. What is the difference between global and detailed routing?

Global routing plans the approximate paths and assigns nets to routing regions to balance congestion. Detailed routing then assigns exact tracks, vias, and metal layers while obeying design rules. Splitting the problem keeps it tractable for millions of nets.

9. What are setup and hold violations in the PD context, and how do you fix each?

A setup violation means the data path is too slow for the clock period; fix it by upsizing cells, reducing buffering on the path, restructuring, or using useful skew. A hold violation means data races through too fast and changes before the capture flop has held it; fix it by adding delay (buffers) on the short path. The crucial detail interviewers listen for: setup is fixed by making the data path faster, hold by making it slower.

10. Why is hold fixed at the fast corner and setup at the slow corner?

Setup is worst when cells are slowest (slow process, low voltage, high temperature in classic CMOS), so you close setup at the slow corner. Hold is worst when cells are fastest (fast process, high voltage), so you verify and fix hold at the fast corner. Multi-corner multi-mode (MCMM) analysis checks all relevant combinations together.

11. What is OCV / on-chip variation, and why does it matter?

Process, voltage, and temperature vary across a single die, so launch and capture paths don't see identical delays. OCV (and its advanced form, AOCV/POCV) applies derating to model this pessimism realistically, preventing chips that pass STA but fail in silicon.

12. What checks make up physical verification?

DRC (design rule checks — spacing, width, density), LVS (layout-versus-schematic, ensuring the layout matches the netlist), antenna checks, and ERC. These gate tape-out; a single unresolved DRC or LVS mismatch blocks the chip.

Static timing analysis essentials

13. What is a timing path, and what are its components?

A path runs from a startpoint (input port or flop clock pin) to an endpoint (flop data pin or output port). Its delay is the sum of clock-to-Q, cell delays, and net delays, checked against the required time set by the clock period and setup/hold constraints. Slack = required − arrival; negative slack is a violation.

14. What is the difference between STA and dynamic timing simulation?

STA is exhaustive and vectorless — it checks every path against constraints without needing test stimulus, which is why it scales to huge designs. Dynamic simulation checks only the paths your vectors exercise but can catch things STA can't model well (like glitches). Signoff relies primarily on STA.

How to prepare for a PD interview

Physical design interviews reward engineers who can connect a symptom to a root cause across the flow: "timing is failing — is it the floorplan, the placement, the clock tree, or the constraints?" That diagnostic instinct only comes from having closed real designs.

A few tips:

• Memorize the RTL-to-GDSII flow so you can narrate it backwards and forwards.
• Be precise about corners. Mixing up which corner fixes setup vs hold is an instant red flag.
• Speak the tool language. Reference timing reports, congestion maps, and SDC constraints concretely.
• Always think signoff. Tie answers back to DRC/LVS/STA closure — that's the job.

The best way to pressure-test your flow knowledge is to be interviewed by someone who signs off chips for a living. On MockVise you can book a mock interview with verified physical design engineers from leading semiconductor companies and get a candid debrief on your timing-closure reasoning and where it would hold up in a real loop.

Know the flow cold, respect the corners, and treat every answer as a step toward tape-out.