Static Timing Analysis (STA) Interview Questions & Answers

Static timing analysis is the language of timing closure. Whether you are interviewing for a physical design, RTL, or timing/signoff role, STA questions are nearly guaranteed — and interviewers use them to separate engineers who understand timing from those who only run the tool. This guide covers the STA questions asked most often, with concise, correct answers.

It pairs naturally with our VLSI physical design guide and the timing sections of our RTL design guide.

Fundamentals

1. What is static timing analysis? A vectorless method that checks every timing path against constraints by summing path delays — no test stimulus required. It's exhaustive and scales to millions of paths, which is why it's the signoff method of choice.

2. STA vs dynamic simulation? STA checks all paths without vectors but can't model functional behavior or glitches; dynamic simulation checks only exercised paths but captures real activity. Signoff relies on STA.

3. What is a timing path? A route from a startpoint (input port or register clock pin) to an endpoint (register data pin or output port). Its delay is compared against the required time.

4. What are the four path types? Input-to-register, register-to-register, register-to-output, and input-to-output (combinational).

Setup, hold, and slack

5. Define setup and hold time. Setup: data must be stable before the clock edge. Hold: data must remain stable after the edge. Violating either risks metastability.

6. Write the setup check. Tclk ≥ Tcq + Tcomb + Tsetup − Tskew. Data must arrive before the next capture edge.

7. Write the hold check. Tcq + Tcomb ≥ Thold + Tskew. Data must not arrive too early and overwrite before the capture flop holds it.

8. What is slack? Slack = Required time − Arrival time. Positive slack passes; negative slack is a violation. Worst negative slack (WNS) and total negative slack (TNS) summarize a design.

9. Why is setup checked on the next edge and hold on the same edge? Setup verifies data launched at edge N arrives before edge N+1; hold verifies data launched at edge N doesn't corrupt the capture of that same edge N.

Clocks and skew

10. What is clock skew? The difference in clock arrival time between launch and capture flops. Positive skew (capture later) helps setup but hurts hold; negative skew is the opposite.

11. What is clock latency / insertion delay? Delay from the clock source to a flop's clock pin. Distinguish network latency (in the tree) from source latency (before the tree).

12. What is clock jitter and how does STA model it? Cycle-to-cycle clock edge variation; modeled as clock uncertainty that eats into the available period.

13. What is useful skew? Intentionally skewing clocks to borrow time from a tight path to a looser neighbor — a closure technique, traded against hold margin.

14. What is time borrowing? With latches (level-sensitive), a path can "borrow" time into the next phase because the latch is transparent — unlike edge-triggered flops.

Exceptions

15. What is a false path? A path that is never functionally exercised (e.g., across an asynchronous boundary or a mutually exclusive mux setting). Declared so STA doesn't waste effort or block closure on it.

16. What is a multicycle path? A path intentionally allowed more than one clock cycle to propagate; you tell STA via a multicycle constraint so it isn't flagged as a violation.

17. Why must false/multicycle paths be set carefully? A wrong exception can mask a real violation, producing silicon that fails. Interviewers probe whether you respect that risk.

18. What is a clock gating check? STA verifies the enable to a clock gate meets setup/hold relative to the clock so the gate doesn't create glitches.

Variation and corners

19. What is OCV / on-chip variation? Process, voltage, and temperature vary across a die, so launch and capture paths see different delays. STA derates paths to model this pessimism.

20. What are AOCV and POCV? Advanced and parametric OCV — less pessimistic, distance/depth-aware derating models that replace flat OCV margins.

21. Why is setup worst at the slow corner and hold at the fast corner? Setup (data too slow) is worst when cells are slowest; hold (data too fast) is worst when cells are fastest. You close each at its worst corner.

22. What is MCMM? Multi-corner multi-mode analysis — checking all relevant corner/mode combinations together (e.g. functional vs test mode across PVT).

23. What is CRPR (clock reconvergence pessimism removal)? Removes double-counted OCV pessimism on the common segment of launch and capture clock paths.

Practical closure

24. A path fails setup — how do you fix it? Upsize/restructure logic, reduce levels, pipeline, use useful skew, or relax the clock. Make the data path faster.

25. A path fails hold — how do you fix it? Add delay (buffers) on the short path. Make the data path slower. Hold fixes rarely cost timing but add area/power.

26. Why fix hold after CTS, not before? Hold depends on the real clock tree; fixing it pre-CTS with estimated skew is unreliable.

27. What is a recovery/removal check? Setup/hold-like checks for asynchronous reset de-assertion relative to the clock, ensuring clean reset release.

How to prepare

STA interviews reward precision. Mixing up which corner fixes setup vs hold, or how skew affects each, is an instant red flag. Tips:

• Memorize the setup and hold inequalities and be able to manipulate them.
• Be exact about corners and skew signs.
• Respect exceptions — always mention the risk that a false/multicycle path can hide real failures.
• Tie answers to closure — interviewers want an engineer who can actually sign off a block.

The fastest way to sharpen this is to be quizzed by someone who closes timing for a living. On MockVise you can book a mock interview with verified timing and physical design engineers and get a candid debrief on exactly where your STA reasoning would hold up in a real signoff review.

Know the inequalities, respect the corners, and treat every path as a step toward clean signoff.