Physical Design Engineer vs STA and Signoff Engineer

You have a recruiter message in one tab that says "Physical Design Engineer" and another that says "STA Engineer." Both mention timing closure and PrimeTime. Are they the same job with different labels, or two different careers? The honest answer is that it depends on the team.

This post compares the two using public Synopsys documentation, a short Wikipedia overview of static timing analysis, and two public NVIDIA job postings. The practice prompts and suggestions are ours, not reported interview questions.

Where do the two roles overlap?

Physical design (PD) takes a netlist through floorplanning, placement, clock tree synthesis (CTS), routing, and engineering change orders (ECOs) until it becomes a layout. STA and signoff checks whether that design meets timing under the conditions the chip must survive. In many companies one person does both, so a title is a weak signal.

Public postings show the blur. One NVIDIA posting for a "Senior Physical Design Full Chip STA Engineer" lists in-depth STA, using PrimeTime to debug paths, interpret constraints, and generate SDC and timing ECOs, and coordinating with physical design, RTL, and DFT teams. It asks for 6 years of hands-on STA experience and lists physical design flow knowledge as a plus. That posting was marked removed in August 2025, so treat it as an example of wording, not an open job.

A second NVIDIA posting, for DFT-focused STA, describes constraints, timing environments, timing models, and timing ECOs at block and full-chip level, with 2 to 3 years of experience. It was marked closed in February 2026. So STA roles can be posted at quite different levels, and some are tied to a specific domain such as DFT.

Search summaries of Glassdoor interview pages for physical design roles at a few large companies also mention setup and hold or STA questions inside PD loops. The sample is small and self-reported, and tells you nothing about any specific team today. It does suggest that a PD candidate should be ready to talk timing. Our timing closure trends post covers the same pressure from the hiring side.

What the daily work tends to look like

PD work is mostly about building and improving a database. You shape a floorplan, place macros, check congestion, build clock trees, route, and then fix what is left. Synopsys describes its implementation tools as aiming for good power, performance, and area results with signoff timing, parasitic extraction, and power analysis built in to reduce iterations. That matches the PD view: you are always trading one metric against another.

Signoff work is mostly about trust in the numbers. Synopsys describes PrimeTime as its signoff solution covering timing, signal integrity, power, and variation, with multi-corner analysis, constraint consistency checks, and physically aware ECO guidance. In a signoff role you spend more time on constraints, corner and mode setup, and questions like "is this violation real, or is the constraint wrong?"

Synopsys also warns that incomplete, inconsistent, or conflicting constraints can keep tools from converging. That is a good reason a signoff engineer reads SDC carefully. A wrong exception can hide a real failure.

Side by side

This table is an editorial summary, built from the sources above and from role concepts. Real teams mix these tasks differently.

	Physical design	STA and signoff
Day-to-day work	Floorplan, placement, CTS, routing, congestion and power grid, fixing violations with ECOs	SDC review, corner and mode setup, path debugging, signoff reports, timing ECO lists
What interviews tend to probe	Flow order, why a floorplan choice helps, skew and useful skew, how you would fix congestion or a hold failure	Setup and hold math, exceptions, OCV, AOCV, POCV, CRPR, why corners differ
Skills to show	Tool flow fluency, Tcl, judgment about PPA tradeoffs	Constraint judgment, variation models, scripting, reading reports skeptically
Who you work with	RTL, library, and CAD teams	PD, RTL, DFT, and CAD teams
Questions to ask	Who owns the floorplan, how often does RTL change late	Who owns the constraints, who approves waivers

What interviews tend to probe

For PD, practice explaining a flow in order and defending choices. Why place macros near the edge? What does CTS do to hold? Our VLSI physical design question guide and the upcoming clock tree and floorplanning questions post cover these.

For STA and signoff, expect more depth on the analysis itself. Wikipedia's overview describes setup violations as a signal arriving too late and hold violations as a signal changing too soon after the clock edge. It also notes that a corner is a specific combination of process, voltage, and temperature, and that corner analysis can be pessimistic when the worst case rarely occurs. Be ready to extend that: why setup and hold have different worst corners, and what an exception can hide. Work through the static timing analysis questions.

Variation is a common deep topic. Synopsys' 2009 white paper describes plain OCV as a flat margin across the chip, and says AOCV derives derates from logic depth or location to reduce excess margin. A 2020 Synopsys blog says POCV is aimed at FinFET designs. A good practice answer explains why a flat margin is pessimistic, then names what a more detailed model needs, such as library support. Do not claim one method is always used, since adoption varies by node and company.

If the posting mentions IR drop or power-aware timing, add power integrity to your list.

How do you decide between them?

Ask yourself what you want to be good at in five years. If you like building the layout and making tradeoffs, PD may fit. If you like analysis, rules, and being the person who says whether a chip meets timing, signoff may fit. Many engineers start in PD and specialize later, and some stay in a hybrid role.

Ask each team plain questions:

1. What would I own in the first six months, in terms of blocks or checks?
2. Who owns constraints and approves waivers?
3. How do PD and signoff engineers share ECO work?
4. What does a late RTL change look like in practice?
5. How is timing debug taught to new people?

Our guide to interviewer questions and the red flags post help you read the answers. To rehearse a path-debug explanation out loud, book a mock interview on MockVise.

Sources: Synopsys PrimeTime, Synopsys PrimeTime technology blog, Synopsys physical implementation, Synopsys Advanced OCV white paper, Wikipedia: Static timing analysis, NVIDIA senior physical design full chip STA posting (Built In), NVIDIA STA engineer posting (Built In), Glassdoor summary (search result): Qualcomm physical design interview page. This is general preparation guidance, not an official process or reported company questions. Vendor pages are marketing material, job postings are examples that may be closed, and candidate reports are anecdotal and may be out of date. Confirm role scope with your recruiter. MockVise is not affiliated with or endorsed by Synopsys, NVIDIA, Qualcomm, Wikipedia, or Built In.

FAQ

Q: Are physical design and STA the same job? In many companies one person does both, and public postings show the blur. At other companies the roles are separate, which is why you should ask the team what you would own.

Q: What do STA and signoff interviews focus on? Expect setup and hold math, exceptions, OCV, AOCV, POCV, CRPR, and why corners differ. Be ready to explain why setup and hold have different worst corners and what an exception can hide.

Q: Why do signoff engineers read SDC so carefully? Incomplete, inconsistent, or conflicting constraints can keep tools from converging. A wrong exception can also hide a real failure.

Q: What should I ask a team before choosing a role? Ask what you would own in the first six months, who owns constraints and approves waivers, how PD and signoff engineers share ECO work, what a late RTL change looks like, and how timing debug is taught to new people.