Low-Power Design Interviews: UPF, Clock Gating, and Power Domains Explained

Someone hands you a block diagram with three boxes and says one of them gets powered off when the chip is idle. What has to be true at its boundary? What happens to its registers? And when it wakes up and misbehaves, where do you look first?

Low-power questions often follow a project you mentioned. This guide draws on Harvey Mudd's public lecture notes for CMOS VLSI Design (Lecture 7: Power), a SiliconPath introduction to UPF, and a Neurealm UPF case study. The practice prompts are ours, not questions reported from any employer.

Are dynamic power and leakage different problems?

The Harvey Mudd notes split total power into dynamic and static parts. Dynamic power comes mainly from switching load capacitances, with a smaller short-circuit component. The notes say short-circuit current is under 10% of dynamic power when input and output rise and fall times are comparable, and then mostly ignore it.

Switching power is written as activity factor times capacitance times supply voltage squared times frequency. A clock has an activity factor of 1, while a signal that switches once per cycle is 1/2. That is why the notes call clock gating the best way to reduce activity: turn off the clock to registers in unused blocks and you remove the clock's switching and all the downstream switching in that block. You do have to know that the block will not be used.

Static power is drawn even when the chip is quiet. The notes list subthreshold, gate, and junction leakage, plus contention current in ratioed circuits. Their levers include multiple threshold voltages and the stack effect (two series OFF transistors leak roughly 10x less).

Name which kind of power you are attacking. Clock gating cuts dynamic power. It does nothing for leakage, because the block is still powered.

What boundary problems does power gating add?

To cut leakage you turn the supply off. The same notes describe power gating this way: use a virtual supply, put a sleep transistor in series, and gate the outputs "to prevent invalid logic levels" reaching the next block. They also list costs. The voltage drop across the sleep transistor hurts performance in normal operation, switching a wide sleep transistor costs dynamic power, and the technique is "only justified when the circuit sleeps long enough."

Volunteer that tradeoff. If a block idles for only a few cycles, power gating probably loses to clock gating.

Three cell types come up next. The SiliconPath guide describes isolation as clamping the outputs of a switched domain to a fixed value while it is off, with the isolation cells powered from an always-on supply. Retention maps selected registers to cells that save state before power-down and restore it afterward, also on an always-on supply. Level shifters translate signals between domains at different voltages. Harvey Mudd's notes add that converters are required when crossing from a low-VDD domain to a high one.

For physical design roles, our physical design interview guide covers the surrounding flow.

What does UPF actually say?

UPF (IEEE 1801) describes power intent in a Tcl-based file separate from the RTL. SiliconPath notes the same RTL can then be reused in chips with different power architectures. Neurealm adds that power-aware simulation can model signals as 0, 1, X, or Z depending on power conditions.

You do not need the full syntax, only what each command is for. The practice prompts in this table are MockVise's suggested exercises, not an employer's rubric.

Topic	Documented distinction	Practice prompt
Power switch	create_power_switch makes a domain switchable through an enable, with a virtual output supply	Who drives the enable, and in which domain does that logic live?
Isolation	set_isolation clamps outputs of a powered-down domain; cells need an always-on supply	What clamp value is safe for an active-low request signal?
Level shifting	set_level_shifter applies only where voltages differ across a boundary	Which crossings need one, and in which direction?
Retention	set_retention picks registers to save and restore, with save and restore controls	What would you retain, and what could you simply reset?
Power states	add_power_state declares legal supply combinations that tools use to find required cells	Which mode combinations does the product actually use?

SiliconPath makes a point worth repeating in an interview: most UPF bugs are not syntax errors but intent errors, such as an isolation strategy that misses one output or a clamp value that asserts a request. Tools can pass these silently.

Where each role gets probed

Our suggested prompts by role are exercises, not a prediction of what you will be asked.

For RTL, practice explaining how you would decide that a block is idle enough to gate its clock, since the Harvey Mudd notes say clock gating "requires determining if block will be used." Our RTL design question guide covers the surrounding fundamentals.

For DFT, practice a question of our own: what should test mode assume about a domain that is powered off, and how would isolation affect observability? The sources here do not answer that, so say where you are unsure. The DFT versus design engineer guide outlines how the roles differ.

For physical design, practice explaining which supply feeds each isolation, retention, and level shifter cell, and why. Supply quality is a related topic, covered in our guide to power integrity and PDN questions.

An illustrative debugging scenario

Here is a scenario of our own, not a reported question: a block works at first boot but fails after it is powered down and back up. Our suggested way to reason through it:

1. Ask what "fails" means: wrong data, a hang, or X values each point to different causes.
2. Check sequencing. Was isolation released only after the supply was stable and the block was out of reset? Was it enabled before the supply dropped?
3. Check retention. Were save and restore asserted in the right order, and is the restored state what the block expects after reset?
4. Check the isolation list against the block's outputs. One missed output, or a clamp that looks like an active request, can cause trouble downstream.
5. Compare the UPF power states against the sequence the firmware runs.
6. Run the static low-power checks after any UPF change, as SiliconPath advises,.

Say which of these you have actually done, and whether it was only in simulation.

To rehearse, book a mock interview on MockVise and talk through a power-down scenario out loud.

Sources: Harvey Mudd College, CMOS VLSI Design Lecture 7: Power, SiliconPath, Neurealm. This article provides general technical preparation guidance, not company interview questions. Interview formats vary, so confirm them with your recruiter. MockVise is not affiliated with or endorsed by Harvey Mudd College, SiliconPath, or Neurealm.

FAQ

Q: When should you use clock gating instead of power gating? If a block idles for only a few cycles, power gating probably loses to clock gating. Power gating is only justified when the circuit sleeps long enough, because the sleep transistor costs performance and dynamic power.

Q: What do isolation, retention, and level shifter cells do? Isolation clamps the outputs of a switched domain to a fixed value while it is off. Retention saves selected registers before power-down and restores them afterward, and level shifters translate signals between domains at different voltages.

Q: Do I need to know full UPF syntax for an interview? No, you need to know what each command is for, such as power switches, isolation, level shifting, retention, and power states. The more useful point is that UPF bugs are usually intent errors, like an isolation strategy that misses one output.

Q: Where do I look first when a block fails after being powered down and back up? Start by asking what fails: wrong data, a hang, or X values point to different causes. Then check sequencing, retention save and restore order, the isolation list against the block outputs, and the UPF power states against the firmware sequence.