PLL and Clocking Interview Questions: Jitter, Phase Noise, and Loop Stability

Someone shows you a phase noise plot and says the integrated jitter is twice what the simulation predicted. Where do you look first? If your answer is "the VCO," you may be right, but you have not yet said why.

PLL and clocking questions come up in SerDes, RF, and mixed-signal conversations alike. This guide draws on UCSB lecture notes on phase locked loops by Prof. S. Long and two Texas Instruments documents: a technical article on loop-filter bandwidth and an application note on the CDCE62005 clock device. The practice prompts are ours, not questions reported from any employer.

Start with the blocks and what each one does

A PLL, as the UCSB notes put it, is a feedback system with a VCO, a phase detector, and a low pass filter in the loop. It forces the VCO to track the phase and frequency of the input. When locked, the frequencies match exactly, though a constant phase offset can remain.

Charge pump PLLs add a loop filter driven by current pulses, and a divider in the feedback path sets the multiplication ratio N. A good practice answer names each block and says what it contributes: the phase detector produces the error, the filter turns pulses into a control voltage, the divider sets N, and the VCO produces the output.

The UCSB notes make one point that is easy to miss. A charge pump with only a capacitor as its loop filter has zero phase margin. Adding a series resistor gives the phase lead you need. Be ready to explain that, because it is a clean way to show you understand stability and not just the block diagram.

What happens inside the loop bandwidth versus outside it?

This is the idea most interviewers return to. According to UCSB, reference noise sees a low-pass transfer function and, for an integer-N loop, gets multiplied by N. VCO noise sees a high-pass transfer function: the loop suppresses it within the loop bandwidth, and it passes unattenuated at offsets beyond.

The TI application note says the same thing in practical terms. Output phase noise follows the input clock and in-band PLL noise up to the loop bandwidth. After that, VCO noise and the output buffer's noise floor dominate.

Phase noise and jitter are two views of the same thing. Jitter is a number you get by integrating phase noise over a stated offset range. The TI note, for example, reports RMS jitter for a 100 MHz clock over 10 kHz to 20 MHz. If someone quotes jitter without the integration range, the number is hard to interpret. The exact conversion formula is in standard references. We have not quoted it here, and you should be ready to write it down yourself.

Is there a best loop bandwidth?

There is no single best loop bandwidth. TI's article says the choice trades off jitter, phase noise, lock time, and spurs. The bandwidth where the PLL and VCO noise curves cross minimizes the area under the combined curve, so it is optimal for jitter, but TI notes it is not optimal for the other three.

In TI's example simulation, the jitter optimum was near 140 kHz. Going wider helped lock time and 10 kHz phase noise, but hurt spurs and phase noise at 1 MHz offset. TI suggests starting at the jitter-optimal bandwidth, then widening for lock time or close-in noise, or narrowing for far-out noise or spurs. That is one device's example, not a universal rule.

The TI application note adds a reference-quality angle. A wider bandwidth is generally recommended when the input clock is clean, such as a crystal or TCXO. A narrower one suits a noisy input that needs jitter cleaning.

Turn the documentation into a study plan

The technical distinctions below come from the sources above. The practice prompts are MockVise's suggested exercises, not an employer's rubric.

Topic	Documented distinction	Practice prompt
Reference noise	Low-pass filtered by the loop and multiplied by N (integer-N)	Why does a high N hurt in-band noise?
VCO noise	High-pass filtered, so suppressed only inside the bandwidth	What does a wider bandwidth do to VCO noise?
Jitter optimum	The PLL and VCO noise crossover minimizes integrated jitter	Why isn't that bandwidth also best for lock time?
Stability	A capacitor-only charge pump filter has zero phase margin; the TI note suggests 50 to 80 degrees	How does a series resistor change the loop?
Reference spurs	A jumpy control voltage modulates the VCO at the reference frequency; a second capacitor filters it but reduces phase margin	What do you give up when you add that pole?

Work through a jitter scenario

Here is an illustrative scenario from us: measured RMS jitter is higher than expected. There is no single answer, but a structured one sounds like this.

1. Confirm the integration range and measurement setup match the specification you are comparing against.
2. Locate the loop bandwidth on the phase noise plot and see whether the excess sits below it or above it.
3. If the excess is in-band, suspect the reference, the phase detector path, or a large N, since reference noise is multiplied by N.
4. If it is out-of-band, suspect the VCO or the output buffer floor, and ask whether a wider bandwidth is allowed.
5. Check for reference spurs (sidebands spaced at the reference frequency) inside the integration range, and for gain peaking near the bandwidth.
6. Change one variable, such as bandwidth, and compare the result against the model.

Real silicon has other contributors, and these sources do not cover them. Say that out loud instead of pretending the two-curve picture is complete.

Prepare your own story

If you have worked on a clocking problem, describe the symptom, the plot you used, and how you decided where the noise came from. If you have not, a simulation or lab exercise works too. Our guides to SerDes eye diagrams, RFIC design interviews, and ADC and DAC questions cover neighboring topics where clock quality matters.

You can also book a mock interview on MockVise to practice explaining a phase noise plot out loud.

Sources: UCSB ECE 594A PLL lecture notes, Texas Instruments SSZTB85, Texas Instruments SCAA113. This article provides general technical preparation guidance, not company interview questions. Formats vary, so confirm the interview structure with your recruiter. MockVise is not affiliated with or endorsed by UCSB or Texas Instruments.

FAQ

Q: Why is a capacitor-only charge pump loop filter a stability problem? The UCSB notes say a charge pump with only a capacitor as its loop filter has zero phase margin. Adding a series resistor gives the phase lead you need.

Q: Why does a jitter number need an integration range? Jitter is obtained by integrating phase noise over a stated offset range. If someone quotes jitter without that range, the number is hard to interpret.

Q: How do you debug RMS jitter that is higher than expected? Find the loop bandwidth on the phase noise plot and see whether the excess sits below or above it. In-band excess points to the reference, the phase detector path, or a large N, while out-of-band excess points to the VCO or the output buffer floor.

Q: When should the loop bandwidth be wider or narrower? A wider bandwidth is generally recommended when the input clock is clean, such as a crystal or TCXO. A narrower one suits a noisy input that needs jitter cleaning.