Analog & Mixed-Signal Design Interview Questions (2026 Guide)

Analog and mixed-signal (AMS) interviews are notoriously deep. Unlike digital roles where you can lean on tools to close timing, analog design rewards intuition built over years, and interviewers probe exactly that intuition. They want to know whether you understand why a circuit behaves the way it does, not just whether you can recite a formula.

This guide walks through the questions that come up again and again for analog, mixed-signal, and SerDes roles at companies like Texas Instruments, Analog Devices, Qualcomm, Broadcom, and Apple. If you also work near the digital boundary, pair this with our RTL design interview guide.

Core device and amplifier fundamentals

1. Walk me through the small-signal model of a MOSFET in saturation.

Start with the transconductance gm = ∂Id/∂Vgs, the output resistance ro = 1/(λ·Id), and the parasitic capacitances (Cgs, Cgd, Cdb). Interviewers want to see that you can derive gain as gm·ro for a common-source stage and explain how each parameter scales with bias current and device size. Mentioning that gm/Id is a process-independent design knob signals real experience.

2. Why is the gm/Id methodology useful?

Because gm/Id maps directly to a transistor's region of operation and efficiency: high gm/Id (weak inversion) gives the most gain per unit current but is slow; low gm/Id (strong inversion) is fast but power-hungry. Designing in the gm/Id space lets you trade speed, power, and gain systematically across process corners rather than guessing W/L by hand.

3. What sets the gain of a single-stage amplifier, and how do you increase it without burning more power?

Gain is gm·R_out. To raise it without more current, increase output resistance with cascoding (stacking devices) rather than increasing bias. The cost is reduced output swing, a classic analog trade-off you should name explicitly.

4. What is the difference between a telescopic and a folded-cascode op-amp?

A telescopic cascode has the highest speed and lowest power but very limited output swing and an input/output common-mode range that overlaps awkwardly. A folded cascode sacrifices some speed and power to decouple input and output common-mode ranges, giving wider swing, which is the usual choice when you need the input near a supply rail.

Feedback, stability, and noise

5. What is phase margin and what value do you target?

Phase margin is how far the loop phase is from −180° at the unity-gain frequency. Below ~45° you get ringing and overshoot; ~60° is the typical sweet spot balancing speed and settling. Too much phase margin means a sluggish, over-damped response.

6. How do you compensate a two-stage op-amp?

Miller compensation: a capacitor across the second stage splits the two poles apart (pole splitting), pushing the dominant pole down and the non-dominant pole up. The subtlety is the right-half-plane zero Miller compensation introduces: you cancel it with a nulling resistor in series with the Miller cap, or use a cascode/feedforward scheme.

7. What are the main noise sources in a CMOS analog circuit?

Thermal noise (from channel resistance, white, 4kTγ/gm) and flicker (1/f) noise, which dominates at low frequencies and scales inversely with device area. The practical takeaways: use larger devices and PMOS inputs to reduce 1/f noise, and increase gm to reduce input-referred thermal noise.

8. What is the difference between noise and offset, and how do you mitigate each?

Offset is a static mismatch (deterministic per chip); noise is random over time. Offset is fought with good layout matching and techniques like auto-zeroing or chopper stabilization. Noise is fought with device sizing, bandwidth limiting, and correlated double sampling. Chopping helpfully attacks both offset and 1/f noise by modulating the signal above the flicker corner.

Data converters and PLLs

9. Compare a SAR, a pipeline, and a delta-sigma ADC.

A SAR ADC is power-efficient and great for medium resolution/medium speed. A pipeline ADC achieves high speed at high resolution but burns power and needs calibration. A delta-sigma ADC trades speed for very high resolution using oversampling and noise shaping, which is ideal for audio and precision sensing. Knowing which you'd pick for a given spec is the real question.

10. What is the quantization noise of an ideal N-bit ADC?

The SNR of an ideal converter is 6.02·N + 1.76 dB. Be ready to explain where the 1.76 comes from (the RMS of uniformly distributed quantization error) and how oversampling by a factor of M improves SNR by 10·log10(M).

11. How does a PLL achieve frequency lock, and what sets its loop bandwidth?

A phase-frequency detector compares reference and feedback phase, a charge pump and loop filter convert that to a control voltage, and a VCO generates the output, divided back down. Loop bandwidth is set by the charge-pump current, divider ratio, and loop-filter components. A wider bandwidth locks faster and suppresses VCO noise but passes more reference spurs, which is the central PLL trade-off.

12. What is jitter, and how does it relate to phase noise?

Jitter is the time-domain variation of clock edges; phase noise is its frequency-domain counterpart. They are linked by integrating the phase-noise spectrum. For SerDes and data converters, jitter directly limits the achievable bit-error-rate or effective number of bits, so designers obsess over the VCO and supply noise that cause it.

How does layout come up in AMS interviews?

13. Why does matching matter, and how do you lay out matched devices?

Random and systematic mismatch sets the offset and accuracy floor of analog circuits. Techniques: common-centroid layout, dummy devices at array edges, identical orientation, and keeping matched devices close to share the same process gradients and temperature. Larger area averages out random mismatch (σ ∝ 1/√(WL)).

14. What is the difference between a power and a ground bounce problem in mixed-signal chips?

Switching digital currents inject noise into shared supply and substrate, corrupting sensitive analog nodes. Mitigations include separate analog/digital supplies and grounds joined at a single star point, guard rings, deep n-well isolation, and careful placement that keeps noisy digital away from quiet analog.

How should you prepare for an AMS interview?

Analog interviews reward derivation under pressure. You will be asked to size a transistor or estimate a pole location on a whiteboard, talking the whole time. A few tips:

• Always state your assumptions (supply, bias current, process) before solving. Interviewers want a structured approach, not a memorized number.
• Draw the small-signal model. Almost every analog question reduces to one. Showing it immediately builds credibility.
• Name the trade-off. Speed vs power vs noise vs area is the eternal analog quadrilateral. Acknowledging it unprompted reads as senior.
• Know your hand-analysis estimates for gain, bandwidth, noise, and phase margin cold, then mention how you'd verify in simulation.

The fastest way to build this fluency is to be grilled by someone who designs AMS circuits for a living. On MockVise you can book a mock interview with verified analog and mixed-signal engineers from top semiconductor companies and get specific feedback on your reasoning, not just your answers.

Analog is a craft. The interview is just the first conversation in that craft, so go show them how you think.

FAQ

Q: What phase margin should I target for a feedback amplifier? Below about 45 degrees you get ringing and overshoot, and about 60 degrees is the typical sweet spot balancing speed and settling. Too much phase margin means a sluggish, over-damped response.

Q: Why is the gm/Id methodology useful? It maps directly to a transistor's region of operation and efficiency. High gm/Id (weak inversion) gives the most gain per unit current but is slow, while low gm/Id (strong inversion) is fast but power-hungry. It lets you trade speed, power, and gain systematically across process corners.

Q: What are the main noise sources in a CMOS analog circuit? Thermal noise, which is white and comes from channel resistance, and flicker (1/f) noise, which dominates at low frequencies and scales inversely with device area. Larger devices and PMOS inputs reduce 1/f noise, and increasing gm reduces input-referred thermal noise.

Q: How do you lay out matched devices? Use common-centroid layout, dummy devices at array edges, and identical orientation, and keep matched devices close so they share process gradients and temperature. Larger area averages out random mismatch.