ADC and DAC Interview Questions: SAR, Delta-Sigma, and Pipeline Trade-Offs

Someone hands you a spec sheet and asks, "Which ADC architecture would you pick?" The wrong move is to name one and start defending it. The better move is to ask what the signal looks like and what the system does with the samples.

This guide draws on TI's public Precision Labs slides on SAR and delta-sigma converters and a DigiKey article on pipeline ADCs. The practice prompts are ours, not questions reported from any employer.

Three architectures, three different bets

A SAR converter samples the input onto a capacitor, then runs a binary search with a capacitive DAC and a comparator. TI compares it to a balance scale: the MSB is decided first and the LSB last. It captures a snapshot in time, which is why TI and DigiKey both describe it as a low-latency or zero-latency choice.

A delta-sigma converter works differently. It samples a 1-bit modulator at a high rate, then filters and decimates. TI defines the oversampling ratio (OSR) as the modulator clock divided by the data rate, and gives a 1 MHz clock with a 60 SPS output as an example (OSR of about 16k). The result is an average over an interval, not a snapshot.

A pipeline ADC chains stages that each resolve one or two bits, subtract, amplify the remainder (DigiKey describes 2x gain in the example), and pass it on. Stages work on different samples at the same time. DigiKey describes sampling rates from a few MSPS to over 1 GSPS, with resolution ranging from 8 bits at the fastest rates to 16 bits at lower ones.

What are the trade-offs between SAR, delta-sigma, and pipeline ADCs?

TI's slides give figures worth remembering with their context attached. They list SAR resolution up to 20 bits and delta-sigma up to 32 bits. They also list low latency for SAR, and say wide-bandwidth delta-sigma has higher latency (the example given is about 55 samples). The slides separate delta-sigma into a DC-optimized kind and a wide-bandwidth kind, and note that the data sheet usually does not say which one you are looking at. You infer it from the digital filter and the sample rate.

On latency, TI says a sinc filter gives roughly 1 to 3 cycles, while a flat-passband filter is high latency (for example, about 50 cycles). DigiKey cites 12.5 clock cycles of core latency for one 16-bit, 370 MSPS pipeline part, so "pipeline" does not mean "low delay."

A table you can drill from

The middle column is drawn from the TI slides and the DigiKey article. The last column is MockVise's suggested practice, not an employer rubric.

Topic	Documented distinction	Practice prompt
SAR	Snapshot conversion, low latency, resolution up to 20 bits in TI's slides	Why does a SAR need a good sample-and-hold and driver?
Delta-sigma	Oversampling, noise shaping, digital filtering, up to 32 bits	What does OSR buy you, and what does it cost?
Pipeline	Concurrent stages, several cycles of latency, from a few MSPS to over 1 GSPS	Why would latency matter in a control loop but not in a receiver?
Quantization noise	Ideal SNR is 6.02N + 1.76 dB, and oversampling adds 10 log(OSR) in TI's slides	Where does the extra 10 log(OSR) come from?
Aliasing	Nyquist frequency is the maximum input without aliasing; delta-sigma digital filters simplify anti-alias design	Which architectures still need an analog anti-alias filter, and why?

One gap to be upfront about: these sources do not define ENOB, SFDR, INL, or DNL. Take those definitions from the converter data sheet or Analog Devices' MT-003 tutorial, which we could not open while writing this. DigiKey does quote SNR and SFDR for example pipeline parts (69.6 dBFS and 88 dBFS for the 16-bit one), which is a good way to practice reading them. The sources also do not cover DAC architectures, so treat that half of the topic as separate study.

Which ADC architecture would you choose for a given spec?

This is an illustrative scenario and our suggestion, not a reported question. Suppose you are asked to pick a converter for motor-phase current sensing: about 12 effective bits, 1 MSPS, a latency budget of one sample, and a tight power budget.

A reasonable walk-through:

1. Restate the spec and ask what is missing. Is it a control loop? What bandwidth matters? Is the budget measured in samples or microseconds?
2. Do the quick arithmetic. Ideal 12-bit SNR is 6.02 x 12 + 1.76, about 74 dB. If you need about 10.5 effective bits, that is roughly 65 dB, leaving room for real-world noise and distortion.
3. Match the latency. The input is a transient that the controller needs immediately. TI lists motor control and closed-loop control among SAR use cases, and says SAR is the best choice when low latency matters.
4. Rule out the others with reasons. A wide-bandwidth delta-sigma adds filter delay. A DC-optimized one is built for low-bandwidth signals. A pipeline part is aimed at higher rates and costs several cycles of latency.
5. Name what the SAR still needs: a driver that can settle the sampling capacitor and an analog anti-alias filter ahead of it.
6. Say what would change your answer. A slow bridge sensor needing 24 bits and low noise points to delta-sigma, where latency hardly matters.

Notice that the arithmetic is simple. The interviewer is usually looking for whether you ask about the signal first.

Prepare your own version

Write one paragraph for each architecture that starts with the application, not the block diagram. Then practice saying "I'm not sure" about a spec you have not used, and explain how you would check it. Our guides to analog and mixed-signal questions and top analog design questions cover the wider topic list. Sampling clock quality is its own conversation, covered in our post on PLL and clocking questions.

You can also book a mock interview on MockVise and practice defending an architecture choice out loud.

Sources: TI Precision Labs, Choosing SAR or Delta-Sigma, TI Precision Labs, SAR and Delta-Sigma Basic Operation, DigiKey, Pipeline ADCs. This article provides general technical preparation guidance, not company interview questions. Interview formats vary, so confirm them with your recruiter. MockVise is not affiliated with or endorsed by Texas Instruments or DigiKey.

FAQ

Q: When should I choose a SAR ADC over delta-sigma? The post's example is motor-phase current sensing, where the controller needs each sample immediately. TI lists motor control and closed-loop control among SAR use cases and says SAR is the best choice when low latency matters. A slow bridge sensor needing 24 bits and low noise points to delta-sigma instead.

Q: Does a pipeline ADC mean low latency? No. DigiKey cites 12.5 clock cycles of core latency for one 16-bit, 370 MSPS pipeline part. Pipeline converters are aimed at higher rates, from a few MSPS to over 1 GSPS, and cost several cycles of delay.

Q: What does oversampling ratio mean for a delta-sigma converter? TI defines the oversampling ratio (OSR) as the modulator clock divided by the data rate. A 1 MHz clock with a 60 SPS output gives an OSR of about 16k. The output is an average over an interval rather than a snapshot.

Q: Does this guide cover ENOB, INL, DNL, or DAC architectures? No. The sources do not define ENOB, SFDR, INL, or DNL, and they do not cover DAC architectures. Take those definitions from the converter data sheet or Analog Devices' MT-003 tutorial, and treat DAC topics as separate study.