Op-Amp Interview Questions: Stability, Noise, and Compensation

You build a unity-gain buffer, hit the step button in simulation, and the output rings for ten cycles before it settles. The interviewer asks one thing: why? If your answer starts with "add a capacitor," you have skipped the part they actually want to hear.

Op-amp questions come up often in analog interviews because one small circuit touches gain, bandwidth, stability, noise, and offset. This guide draws on a Texas Instruments article on op-amp stability, two Georgia Tech lecture handouts on compensating two-stage op amps, and a TI application report on noise. The practice prompts are ours, not questions reported from any employer.

Start with the loop, not the amplifier

Every stability question is really a question about the loop gain, the open-loop gain multiplied by the feedback factor. Georgia Tech's ECE 6412 notes (Prof. Allen) define phase margin as the phase of that loop gain at the frequency where its magnitude reaches one, and note that a stable negative feedback system needs the phase to stay above zero degrees there. The TI article describes the same thing from the output side: phase margin is how far the total phase shift sits from 360 degrees when closed-loop gain drops below unity.

A clean answer has three pieces. Open-loop gain falls at 20 dB per decade after the dominant pole. The feedback network sets where the loop gain crosses unity, which is why a high-gain configuration is easier to stabilize than a unity-gain buffer. And any extra pole near that crossover, from a load capacitor or a second stage, eats phase margin. Draw the Bode plot while you say it.

How much phase margin is enough?

Expect this one. The TI article says rules of thumb range from 30 to 45 to 60 degrees and then tests the question with a simulation. It models a Miller-compensated op amp with a 1 MHz unity-gain bandwidth and varies the Miller capacitor by 40 percent, output impedance by 15 percent, load capacitance by 10 percent, and load resistance by 5 percent. Starting from a nominal 45 degrees, the 5,000-run Monte Carlo result had a mean near 45 and a minimum of 19 degrees. The author concludes the circuit stays stable with roughly 27 degrees of nominal margin, but that 45 degrees gives good settling and limits overshoot across variation.

The useful move is to connect the number to something physical: process spread moves the dominant pole, which moves unity-gain bandwidth, which moves your margin. Overshoot and settling time both get worse as margin shrinks.

How does Miller compensation work in a two-stage amplifier?

Allen's lecture notes model the two-stage amplifier with a compensation capacitor Cc across the second stage. Three roots matter. The Miller capacitor creates a dominant pole near -1 over (gm6 times R1 times R2 times Cc) in his notation, which is the pole splitting effect. The output pole sits near gm6 over the load capacitance. And a right-half-plane zero appears at gm6 over Cc, which the notes call very undesirable because it raises magnitude while adding phase lag.

The unity-gain bandwidth works out to GB equal to gm1 over Cc. In the second handout, Allen shows that with no zero in play, the output pole must sit above GB for 45 degrees and above about 1.73 times GB for 60 degrees. With the zero pushed to ten times GB, the requirements rise to roughly 1.22 and 2.2 times GB. His fixes for the zero are a unity-gain buffer in the compensation path, or a nulling resistor in series with Cc that can move the zero into the left half plane.

Be ready for follow-ups on slew rate (tail current charging Cc is the usual textbook answer, though these notes are not our source for it) and on why you might choose a folded cascode over a two-stage design. Say what you give up in each case rather than ranking topologies.

Noise, offset, and common-mode

TI's application report on op-amp noise treats noise as a spectral density that you integrate over bandwidth, and it separates thermal, shot, and flicker sources. Its worked example finds the 1/f corner of a TLV2772 from datasheet values (about 12 nanovolts per root hertz of white noise, 130 at 10 Hz) and gets a corner near 1.2 kHz. It also refers resistor noise to the input by dividing output noise by the circuit's noise gain.

For offset and common-mode questions, we suggest this framing: systematic offset comes from the circuit and random offset from mismatch, and common-mode rejection degrades with frequency and mismatch. Our top analog design questions post covers the differential pair side in more detail.

Topic	What the source says	Practice prompt
Phase margin	TI simulates a 45 degree design and finds a 19 degree minimum across variation	Why would you design for more than the minimum stable margin?
Miller pole splitting	Allen: GB is gm1 over Cc, with a dominant pole set by Cc	What happens to GB and the second pole if you double Cc?
RHP zero	Allen: zero at gm6 over Cc adds phase lag and gain	Name two ways to remove or move it
Capacitive load	TI: an isolation resistor adds a zero and costs DC accuracy under load	When would you reach for dual feedback instead?
Noise corner	TI report: corner found where 1/f meets white noise	How would you lower integrated noise without changing the op amp?

An illustrative scenario: the ringing buffer

This is a made-up scenario for practice, not a reported question. A unity-gain buffer drives the sampling input of an ADC, with a large capacitor on the output. Simulation shows heavy ringing on a step.

1. Restate the symptom: ringing means low phase margin at the loop gain crossover.
2. Break the loop and plot open-loop gain and phase, checking where the crossover lands.
3. Identify the extra pole: the op amp's output impedance and the load capacitor form a pole near crossover.
4. Propose the smallest fix: TI describes placing a resistor between the loop and the load capacitor so a zero cancels the added phase lag, and notes that the DC error equals Riso times load current.
5. Check the fix across process and temperature, not only at nominal.

If the converter side is new to you, our ADC and DAC interview questions guide covers what that load looks like. The same loop reasoning shows up in PLL stability questions, and the related LDO and PMIC interview questions apply it to regulators.

Practice and next steps

Pick one amplifier you can draw from memory and derive its poles, zero, and GB from scratch, then say it aloud in two minutes. Our analog mixed-signal question guide widens the set, and you can book a mock interview on MockVise to rehearse the ringing-buffer walkthrough with someone asking follow-ups.

Sources: TI SLYT858, Georgia Tech ECE 6412 Lecture 120, Georgia Tech ECE 6412 Lecture 130, TI SLVA043. This article is general technical preparation guidance, not an official interview process or reported company questions. Verify formulas against the original documents and confirm the interview format with your recruiter. MockVise is not affiliated with or endorsed by Texas Instruments or Georgia Tech.

FAQ

Q: How much phase margin should an op-amp design have? Rules of thumb range from 30 to 45 to 60 degrees. In TI's simulation, a 45 degree nominal design had a 19 degree minimum across variation, and the author concludes 45 degrees gives good settling and limits overshoot.

Q: Why is a right-half-plane zero a problem in a two-stage op amp? It appears at gm6 over Cc and raises magnitude while adding phase lag, which the notes call very undesirable. Fixes are a unity-gain buffer in the compensation path or a nulling resistor in series with Cc.

Q: How do you debug a ringing unity-gain buffer? Ringing means low phase margin at the loop gain crossover, so break the loop, plot open-loop gain and phase, and find the extra pole from the output impedance and load capacitor. Then propose the smallest fix, such as a resistor between the loop and the load capacitor, and check it across process and temperature.

Q: Why is a high-gain configuration easier to stabilize than a unity-gain buffer? The feedback network sets where the loop gain crosses unity, and any extra pole near that crossover eats phase margin. That is why a high-gain configuration is easier to stabilize.