Top 50 Analog Design Interview Questions (With Answers)

This is the question bank we wish every analog candidate had before walking into an IC design loop. It is deliberately broad: 50 questions spanning devices, amplifiers, references, feedback, and noise, so you can self-test and find your weak spots fast. For the mixed-signal and data-converter side (ADCs, PLLs, sampling), pair this with our analog & mixed-signal guide. If radio frequency is your target, see the RFIC design guide.

Answers here are intentionally compact. In a real interview, expect every one to be followed by "why?" and "what's the trade-off?"

Devices and operating regions

1. Draw the I-V curve of a MOSFET and label the regions. Cutoff, triode (linear), and saturation. Be ready to state the boundary Vds = Vgs − Vth.
2. What is threshold voltage and what shifts it? Body effect, temperature, and process. Vth rises with reverse body bias.
3. Saturation current equation? Id = ½·μCox·(W/L)·(Vgs−Vth)²·(1+λVds).
4. What is channel-length modulation? The λ term: finite output resistance from the effective channel shortening with Vds.
5. Define gm, gds, and intrinsic gain. gm = ∂Id/∂Vgs, gds = 1/ro, intrinsic gain = gm/gds = gm·ro.
6. What is the body effect? Source-to-body voltage modulates Vth via gmb.
7. Weak vs strong inversion? Weak (subthreshold) gives high gm/Id, exponential I-V, low speed; strong inversion is the opposite.

Single-stage amplifiers

8. Gain of a common-source stage? −gm·(ro‖RL).
9. Common-gate: what's it good for? Low input impedance, good for current buffering and high-frequency (no Miller effect).
10. Source follower characteristics? Gain ≈ 1, high input/low output impedance, level shifting; suffers from body effect and limited swing.
11. What is the Miller effect? Feedback capacitance Cgd is amplified by the stage gain, lowering bandwidth.
12. Why cascode? Boosts output resistance (gm·ro higher) and shields the input device from Vds swing, reducing Miller.
13. Downside of cascoding? Reduced output voltage swing.
14. Telescopic vs folded cascode? Telescopic: faster, lower power, limited swing/common-mode; folded: wider input common-mode range, more power.

Current mirrors and biasing

15. How does a basic current mirror work? Matched devices share Vgs; output copies the reference current scaled by W/L.
16. What limits mirror accuracy? Vds mismatch (channel-length modulation) and device mismatch.
17. Why a cascode mirror? Higher output impedance → better copy accuracy across output voltage.
18. What is a Wilson mirror? A feedback mirror with high output resistance and good accuracy.
19. How do you make a current reference independent of supply? A constant-gm (Vth-referenced or gm-referenced) bias with a degeneration resistor.

Voltage references

20. What is a bandgap reference and why ~1.2 V? It sums a CTAT (VBE) and a PTAT voltage to cancel temperature drift; the zero-TC point lands near silicon's bandgap voltage.
21. What is PTAT and how is it generated? Proportional-to-absolute-temperature; from the ΔVBE of two BJTs at different current densities.
22. Sources of bandgap error? Op-amp offset, resistor mismatch, and curvature (higher-order TC).
23. What is a brokaw bandgap cell? A classic topology producing both a reference voltage and a PTAT current.

Feedback and stability

24. Four feedback topologies? Series-shunt, shunt-shunt, series-series, shunt-series. Each sets input/output impedance differently.
25. What is loop gain and why does it matter? T = A·β; large T desensitizes gain to device variation and reduces distortion.
26. Define phase margin and a good target. Distance of loop phase from −180° at unity-gain crossover; ~60° is ideal.
27. What causes instability? Two or more poles near the crossover frequency creating excess phase shift.
28. Miller compensation: how does it stabilize a two-stage op-amp? Pole splitting: dominant pole moves down, non-dominant up.
29. The right-half-plane zero problem? Miller cap feeds forward; cancel with a nulling resistor or cascode compensation.
30. What is slew rate and what sets it? Max dV/dt = I/C; limited by tail current charging the compensation/load cap.
31. Gain-bandwidth product? For a dominant-pole amp, GBW = gm/(2π·Cc).

Op-amp design specifics

32. What sets the input common-mode range? Headroom of the input pair and tail current source.
33. What is CMRR and what degrades it? Common-mode rejection; degraded by tail-source finite output resistance and mismatch.
34. What is PSRR? Power-supply rejection; how supply noise leaks to the output.
35. Why use a differential pair? Rejects common-mode, doubles signal handling, improves linearity and PSRR.
36. What is offset and where does it come from? Static mismatch in threshold, W/L, and load; random and systematic.
37. How do you reduce offset? Larger devices, good layout matching, auto-zeroing, or chopper stabilization.

What noise questions come up?

38. Two dominant noise types in CMOS? Thermal (white) and flicker (1/f).
39. Input-referred thermal noise of a MOS? ≈ 4kTγ/gm. Raise gm to lower it.
40. How to reduce 1/f noise? Larger device area, PMOS inputs, chopping, or correlated double sampling.
41. What is the noise corner frequency? Where 1/f noise equals thermal noise.
42. Why does chopping help both offset and 1/f? It modulates the signal above the flicker corner, then demodulates, leaving offset/1-f as high-frequency content to filter.

Why does layout matter in analog interviews?

43. Why does matching require common-centroid layout? It averages out linear process and temperature gradients.
44. What are dummy devices for? Equalizing edge effects so matched devices see identical surroundings.
45. How does device area relate to mismatch? σ ∝ 1/√(WL). Bigger averages out random mismatch.
46. What is antenna effect? Charge accumulation on metal during fab damaging thin gate oxide; fixed with antenna diodes/jumps.
47. Why guard rings? Collect substrate noise/latch-up current and isolate sensitive nodes.

Systems thinking

48. Walk me through sizing a simple amplifier to a gain and bandwidth spec. Pick gm/Id for efficiency, set gm from bandwidth/noise, then W/L and bias current; check swing and phase margin.
49. How do you verify across PVT? Corner and Monte Carlo simulation across process, voltage, temperature, plus mismatch.
50. What's the difference between hand analysis and simulation? Hand analysis builds intuition and a starting point; simulation refines and validates. Interviewers want both.

How should you prepare?

Fifty questions is a checklist, not a strategy. Analog interviews are won by deriving on a whiteboard while narrating your reasoning. Drill the small-signal model until it's automatic, always state your bias assumptions, and name the speed/power/noise/area trade-off on every answer.

The fastest way to expose your gaps is to be grilled by a working analog designer. On MockVise you can book a mock interview with verified analog and IC design engineers and get targeted feedback on exactly which of these 50 you fumbled, and why.

FAQ

Q: What topics do analog design interviews cover? This question bank spans devices and operating regions, single-stage amplifiers, current mirrors and biasing, voltage references, feedback and stability, op-amp specifics, noise, layout, and systems thinking.

Q: How detailed should my answers be? The answers here are compact on purpose. In a real interview, expect each one to be followed by "why?" and "what's the trade-off?"

Q: Where do I find mixed-signal or RF questions? The ADC, PLL, and sampling side is covered in the analog and mixed-signal guide, and radio frequency is covered in the RFIC design guide.

Q: How do I find my weak spots? Fifty questions work as a checklist for self-testing. Being grilled by a working analog designer, for example in a mock interview, exposes which ones you fumbled and why.