Google TPU and Custom Silicon: How to Prepare

You get a recruiter note saying the team works on "TPU." Is that a matrix unit, a memory system, a network between chips, or something else entirely? If you cannot say which part of the stack the role touches, you will struggle to pick what to study.

This guide is a companion to our general Google hardware engineer interview process guide. It goes deeper on the silicon itself, using Google Cloud's TPU documentation, Google's announcements for Ironwood, Axion, and Tensor G5, and two published papers. Practice prompts are ours, not reported questions.

Does Google make more than one kind of chip?

Google describes several separate silicon efforts in public, and they pull in different skills.

TPUs are, in Google Cloud's words, application-specific integrated circuits designed for machine learning. Axion is Google's first custom Arm-based data center CPU, built on Arm's Neoverse V2 cores and paired with Titanium, a system of custom microcontrollers and offloads for networking, security, and storage I/O. Tensor G5 is the phone processor in Pixel 10, which Google says is made on TSMC's 3 nm process. And Google's video coding unit, nicknamed Argos in press coverage, is a transcoding accelerator described in an ASPLOS 2021 paper.

A job titled "ASIC engineer" could sit on any of these. Read the posting for the product name before you decide what to review. Our comparison of mobile SoC and data center chip careers covers how different those days can be.

What Google's TPU documentation gives you

The Cloud TPU architecture page is the best free study guide for this topic. It says a TPU chip has one or more TensorCores, and each TensorCore has matrix-multiply units (MXUs), a vector unit, and a scalar unit. An MXU is a systolic array of multiply-accumulators: 128 by 128 on versions before v6e, and 256 by 256 on v6e and TPU7x. Inputs are bfloat16 and accumulation is FP32. The vector unit handles things like activations and softmax, and the scalar unit handles control flow and address calculation.

The page also covers SparseCores (dataflow processors for embedding-heavy models), HBM, inter-chip interconnect (ICI), pods, slices, and topologies such as 4x4x8. The ICI resiliency feature routes around optical link and switch faults. That detail is a good reminder that this is a systems job as much as a datapath job.

For the same ideas at paper depth, the TPU v4 paper reports optical circuit switches, SparseCores, and a twisted 3D torus option. Its performance comparisons are the authors' own, so treat them as claims, not benchmarks you can repeat.

A reading list that maps to likely discussion topics

Topic	What Google says publicly	What to prepare or ask
Matrix compute	MXUs are systolic arrays, 256 by 256 on v6e and TPU7x	Explain dataflow, utilization, and why bfloat16 inputs with FP32 accumulation
Memory	The TPU loads inputs from HBM and parameters into the MXUs	Sketch where bandwidth runs out first
Scale-out	Slices connect chips with ICI, and Multislice uses the data center network	Ask how the team thinks about failure and availability
Inference focus	Google calls Ironwood its first TPU designed specifically for inference, with 192 GB HBM per chip	Compare what training and inference each demand
CPU and offload	Axion pairs Neoverse V2 cores with Titanium offloads	Ask whether the role is core, uncore, or platform
Fixed-function blocks	The video coding unit reports 20 to 33 times better efficiency than a software baseline	Discuss when a fixed-function block beats programmable hardware
Mobile	Tensor G5 on 3 nm with a new image signal processor	Ask about power and thermal limits in a phone

Ironwood's per-chip figures (4,614 TFLOPs peak, 7.37 TB/s of HBM bandwidth) come from Google's April 2025 announcement and are vendor claims. For the memory side of these questions, our upcoming guide to AI accelerator interview questions on dataflow and bandwidth.

What Google's careers pages show

Google's "How we hire" page, as we could read it, lists "Hiring process" and "Interview prep" sections but did not describe stages for us to summarize. We cannot tell you the TPU loop from official material.

Search results for Google Careers postings (we could not read the full pages, so this is from result summaries) suggest TPU related ASIC roles ask for Verilog or SystemVerilog across levels. Verification postings mention UVM, assertions, and formal methods, and design postings mention scripting and synthesis or PPA experience. Required experience varies by role and level. That fits what you would expect, but read the exact posting you are applying to.

What candidates report (anecdotal)

Community reports are sparse. A search of Glassdoor and Blind turned up a handful of Google ASIC design and verification threads, none clearly from TPU teams, and most a few years old. Summaries describe SystemVerilog coding in a shared document, UVM concepts such as sequencer and driver connections, FIFO and clock domain crossing design, FSMs, and basic timing. One Blind thread about a TPU physical design interview described conceptual questions about place and route stages and power domains. One reviewer thought the interviewer cared more about syntax than logic.

Treat all of that as a small, self-selected sample that may be out of date. It does not tell you what your interviewers will ask. We also did not use pay data: figures on levels.fyi differ between its own pages and mix several hardware titles, so check the level and location you care about yourself.

How should you prepare for a Google silicon interview?

Pick a track and go one layer deeper than your résumé. Our UVM guide and chiplets and packaging guide cover two areas that sit close to accelerator work. If training versus inference design interests you, the upcoming training chip versus inference chip comparison is a useful follow up.

Here are three practice prompts of ours:

1. Walk through how one multiply-accumulate result moves through a systolic array, and where you would add buffering.
2. A block meets timing in one corner and misses in another. What do you check first?
3. Explain a chip you worked on in terms of what it did not do, and why.

In the loop, ask your recruiter which product and which part of the stack the team owns. Our week before an onsite checklist and list of red flags in interviews can help you plan your questions. You can also book a mock interview on MockVise to practice explaining a datapath out loud.

Sources: Google Cloud TPU architecture, Google Ironwood announcement, Google Axion announcement, Google Tensor G5 announcement, TPU v4 paper, Warehouse-Scale Video Acceleration (Google Research), Google Careers how we hire, Glassdoor and Blind summaries (search results). This article is general preparation guidance, not an official Google process or a list of reported questions. Candidate reports are anecdotal and may be out of date, and performance figures are vendor claims. Confirm details with your recruiter. MockVise is not affiliated with or endorsed by Google, Arm, TSMC, Glassdoor, Blind, or levels.fyi.

FAQ

Q: Does Google publish what the TPU interview loop looks like? No. Google's "How we hire" page lists hiring process and interview prep sections but did not describe stages, so the TPU loop cannot be told from official material.

Q: What is the best free resource for studying TPU hardware? The Cloud TPU architecture page. It covers TensorCores, MXUs, the vector and scalar units, SparseCores, HBM, and inter-chip interconnect. For paper depth, read the TPU v4 paper, and treat its performance comparisons as the authors' own claims.

Q: What should I ask my recruiter? Ask which product and which part of the stack the team owns. A job titled "ASIC engineer" could sit on a TPU, a data center CPU, a phone processor, or a video chip.

Q: How reliable are candidate reports about Google ASIC interviews? Not very. They are a small, self-selected sample, none clearly from TPU teams, and most are a few years old, so they do not tell you what your interviewers will ask.