DDR and Memory Controller Interview Questions

Someone hands you a memory trace and says the DDR channel is only delivering a fraction of its peak bandwidth. Where do you look first?

This guide uses two University of Utah lecture decks on DRAM basics and memory controllers, a public Micron DDR4 datasheet, and a community wiki page on memory training. The practice prompts are ours, not questions reported from any employer.

Start with the hierarchy

The Utah lecture describes the structure from the outside in: a memory channel connects the controller to DIMMs, a DIMM holds one or more ranks, a rank is built from several DRAM chips, and each chip has banks, each bank an array of rows and columns. Its example array is 4096 by 4096 bits, with 12 row address bits arriving first and 12 column bits next. A rank might be eight x8 chips side by side, giving a 64-bit data bus.

The detail interviewers like is the row buffer. The lecture notes that activating a row reads a wide row into the sense amplifiers (it gives 8KB for a 64B request as an example), and that the row buffer then acts like a small cache inside the DRAM. So opening a row is expensive, reading an open row is cheap, and different banks can work on different rows at once.

If you are preparing for a memory company, pair this with our overview of memory design interviews at Micron, SK hynix, and Samsung, since "controller" and "array" roles ask quite different things.

Know the timing parameters by what they cost

Attach each parameter to an access type instead of memorizing definitions. The Utah controller slides give a first order model: a row hit costs about tCAS (the notes' name for CL), an access to a closed bank costs tRCD plus tCAS, and a row conflict costs tRP plus tRCD plus tCAS. The DRAM basics deck gives rough figures of about 20 ns, 40 ns, and 60 ns for hit, empty, and conflict, plus queueing and transfer time on top.

The Micron DDR4 datasheet lists DDR4-3200 speed bins with CL, tRCD, and tRP of 22-22-22 clocks, and an internal read to first data time (tAA) of 13.75 ns for the faster bins. The datasheet also lists tRAS (activate to precharge) and tRC (activate to activate). A separate explainer at systemverilog.io covers the bank group rules: tRRD and tCCD are shorter across bank groups (the "S" versions) than within one (the "L" versions), and tFAW caps how many activates fit in a window.

How does a controller schedule refresh?

DRAM cells lose charge, so the controller has to issue refresh commands. The same datasheet gives tREFI, the average refresh interval, as 7.8 microseconds up to 85 C and 3.9 microseconds above that range, and lists tRFC (the time a refresh occupies the rank) as 350 ns for the 8Gb and 16Gb parts. Dividing those two numbers is our arithmetic, not the datasheet's: about 4.5 percent of time at the cooler setting, roughly double when hot.

The systemverilog.io explainer notes that tREFI is an average, so refreshes can be postponed or pulled in. That is a scheduler decision: refresh when the queue is quiet, do not fall too far behind, and precharge open rows first.

Why does a memory controller need training?

The librecore wiki describes memory training as tuning timing so that command, address, clock, data, and strobe signals line up, and says each board and DIMM differs enough that it has to be done per system. It lists write leveling (aligning the clock and strobe, motivated by fly-by routing skew), read training, command and address training, and output drive and ZQ calibration. The page says some sections are incomplete, so use it for orientation only.

Conceptually, an interviewer wants to hear why a fixed delay cannot work and that training is a sequence with dependencies. Our SerDes eye diagram guide covers a similar margin-hunting mindset, and SerDes design versus memory interface PHY design compares the two jobs.

Study table

Topic	What the sources say	Practice prompt
Row buffer	Row hit costs about CL, conflict costs tRP plus tRCD plus CL	Rank hit, empty, and conflict, and say what your controller does to get more hits
Page policy	Break-even hit rate is tRP over tRP plus tRCD, 50 percent when equal	When would you close pages eagerly?
Address mapping	Row, bank, rank, channel bits are fixed at design time	Which bits go low to spread a sequential stream?
Bank groups	Same-group spacing (L) is longer than cross-group (S)	How does that change scheduling?
Refresh	tREFI is an average, tRFC blocks the rank	How do you hide it?
Training	Align clock, strobe, and data per system	What breaks if you skip it?

An illustrative bad access pattern

This scenario uses the DDR4-3200 numbers above and is a simplification, not a measurement. A 64-bit channel at 3200 MT/s moves a 64B burst in about 2.5 ns on the bus. Suppose a program strides through memory so every request lands in the same bank but a different row.

1. Each request finds the wrong row open, so it pays a precharge, an activate, and a read: three times 13.75 ns, about 41 ns.
2. If the controller cannot overlap these, the bus is busy about 2.5 of every 41 ns, roughly 6 percent of peak.
3. The fix is rarely a faster clock. Change the address mapping so consecutive requests spread across banks and bank groups, so activates overlap, within the tRRD and tFAW limits.
4. If the pattern is truly random, a closed page policy may waste less time than keeping rows open.

Then discuss the tradeoff: reordering for row hits raises throughput but can starve a request, and the Utah slides list fairness as a controller requirement. A cache coherence and memory system discussion is a natural next topic, since cache misses generate this traffic. For accelerators, see dataflow, memory bandwidth, and systolic arrays.

Prepare your answer

Practice saying the model first (the three access costs), then the exceptions: bank groups, refresh, and mapping. Use our two week plan to schedule the review, and book a mock interview on MockVise to defend a scheduling choice out loud.

Sources: University of Utah CS7810 DRAM basics, University of Utah CS7810 DRAM memory controllers, Micron 16Gb DDR4 SDRAM datasheet (NXP community copy), systemverilog.io DDR4 timing parameters, librecore wiki on DDR training. This article is general technical preparation guidance, not an official process or reported company questions. Lecture notes use older DRAM generations in places, and datasheet values differ by part and speed grade, so check the standard and datasheet for your target. Confirm interview details with your recruiter. MockVise is not affiliated with or endorsed by Micron, the University of Utah, NXP, or the librecore project.

FAQ

Q: Why does a DDR channel deliver only a fraction of its peak bandwidth? In the illustrative example, a stride that hits the same bank with a different row each time forces a precharge, an activate, and a read per request, leaving the bus busy about 6 percent of the time. The fix is usually address mapping that spreads requests across banks and bank groups, not a faster clock.

Q: Why is a row hit cheaper than a row conflict? Activating a row reads it into the sense amplifiers, where the row buffer acts like a small cache. A hit reads the open row, while a conflict pays precharge, activate, and read.

Q: How much time does refresh cost? Using the datasheet's tREFI of 7.8 microseconds and tRFC of 350 ns, the article's own arithmetic gives about 4.5 percent of time at the cooler setting and roughly double when hot. Because tREFI is an average, a scheduler can postpone or pull in refreshes.

Q: Why can't a fixed delay replace memory training? Each board and DIMM differs enough that timing has to be tuned per system. Training is a sequence with dependencies: write leveling, read training, command and address training, and output drive and ZQ calibration.